Computer memory technology has experienced profound advances in the last two decades. One of the first computer memories involved magnetic core memory technology. To form each magnetic core, a miniature toroidal-shaped ferrite core was interwoven into a fine matrix of wires. By applying a current through the wires, th core would be programmed with either a north or south direct flux path that would correspond to a logic one or zero. The advantage of magnetic core memory is that it is non-volatile, or does not need to be refreshed to remembered the store logical signal. Additionally, core memory is also “radiation-hard” or unaffected by ionizing radiation like gamma rays. However, the assembly of the magnetic core array was very labor intensive and was quickly abandoned when semiconductor processes were developed.
Currently one of the most popular memory technologies uses either a form of MOS (metal-oxide-semiconductor) or CMOS (complementary metal-oxide-semiconductor) processes. However, it is well known that this technology requires constant refreshing of each memory cell to maintain the logic signal strength due to the inherent leakage of capacitors. The constant refreshing of the memory cells is not a problem when there is an unlimited voltage source, but in many applications, like laptop computers and cell phones, there is a finite supply. To deal with this problem, rechargeable batteries have been used in all portable electrical devices.
The problem with using devices that have capacitive memory arrays is the inconvenience in keeping the batteries properly charged every few hours. Therefore, there is a need for a non-volatile memory device that does not need to be refreshed and is inexpensive and quick to make. Additionally, in a ferromagnetic memory array, it has generally been necessary to provide a wholly separate circuit to detect the polarity, and thus the binary value, of the remnant magnetic field of a ferromagnetic digital memory cell. For example, many current ferromagnetic memories use such techniques as “giant magneto resistance” and the Hall effect to sense the magnetic polarity of memory bits. These require circuitry in addition to that used for state change, and in some cases many extra steps to fabricate. The requirement of a separate sensing circuit adds considerably to the time and expense of fabrication. This additional circuitry also limits the density of the memory cells in an array, and effects the time required to read, or sense the magnetic polarity, or value.
In the digital memory arena, especially random access memory, fast, dense non-volatility is an advantage. Accordingly, it is desirable to have a non-volatile memory array wherein the remnant magnetic field is sensed with the same circuitry used to write, or effect the state change of, a ferromagnetic bit in such a memory cell.
Examples of patents related to non-volatile RAM, each of which are herein incorporated by reference for their supporting teachings, are as follows:
U.S. Pat. No. 4,360,899 to Dimyan et al. teaches a non-volatile random access memory having a plurality of magnetic cells arranged in an array on a major surface of a substrate. In operation, a single magnetic cell is selected and inductively switched between opposite remnant, (i.e. permanent) states, upon the simultaneous application of electrical pulses to a pair of conductors intersecting adjacent the selected cell. Each electrical pulse has an amplitude which is insufficient to inductively switch the remnant state of the selected cell. However, the combined amplitude of the electrical pulses is at least equal to the amplitude required for such a switch.
U.S. Pat. No. 5,068,826 to Mathews teaches a non-volatile, static magnetic memory device, whose operation is based on the Hall effect The device includes a magnetic patch which stores data in the form of a magnetic field, a semiconductor Hall bar, and a pair of integrally-formed bipolar transistors which are used for amplifying and buffering the Hall voltage produced along the Hall bar. In use, current is forced to flow down the length of the Hall bar causing a Hall voltage to be developed in a direction transverse to the direction of both the magnetic field and the current. The bases of the bipolar transistors are ohmically coupled to the Hall bar to sense the Hall voltage-the polarity of which is representative of the stored information Finally, a system of current carrying conductors is employed for writing data to individual magnetic patches.
U.S. Pat. No. 5,295,097 to Lienau teaches a non-volatile random access memory having a substrate that carries separate magnetically polarizable domains. Each domain is surrounded by a full write loop member, and arranged to penetrate a Hall channel of a dual drain FET with its residual magnetic field. The domains are organized in word rows and bit columns, are each written to by a single full write current through the surrounding loop member, and each read by a comparator connected to the FET drains. Independent separate write lines and read lines are used in writing and reading the values of each magnetic bit.
U.S. Pat. No. 4,791,604 to Lienau et al. teaches a sheet random access memory (SHRAM). The SHRAM is a non-volatile and transportable memory characterized by its cell density and relatively small size and power requirements, but having the non-volatile character and rugged transportability of core memory, or magnetic disks or tape. The SHRAM is further characterized by a memory comprising a two dimensional magnetic substrate and a fixed driving device for writing and reading into the substrate. Further, a fixed sensing device for sensing the information is attached at each cell location. The memory media includes not only a homogeneous two dimensional substrate, but also ferrite cores formed into the substrate by photolithographic techniques, wherein the information is stored within the core and read by the sensing device from a gap by the core. Memory cells according to the invention can thus be arranged and organized to form destructive readout RAMs, or nondestructive readout rams in both serial and parallel form.
U.S. Pat. No. 6,229,729 to Lienau teaches a non-volatile RAM device which utilizes a plurality of ferromagnetic bits each surrounded by a write coil for directing the remnant polarity thereof is disclosed. The direction of magnetic remnance in each bit is dictated by the direction of a current induced into write coil. Further, a magneto sensor comprising a magneto resistor coupled to a diode is placed approximate each bit. The magneto resistor is coupled to a sense line, and receives current at a first point of attachment, and returns current at a second point of attachment. The current passing across magnetic resistor is biased in a direction either right or left of the original current flow direction. If current is biased toward the anode end of diode then it is complimentary to the preferred flow direction of diode, and flows easily there across. The ultimate effect is that the serial resistance of magneto resistor is reduced, allowing a greater a of current to pass into the sense line. When current is biased toward the cathode end of diode, then it is contrary to the preferred flow direction of the diode and does not flow easily there across. The ultimate effect is that the serial resistance of magneto resistor is increased, allowing a smaller amount of current to pass into sense line. The presence and amount of current found in the sense line between the bit and the detector determines whether a digital value of “1” or “0” is stored in the magnetic bit. A method for storing binary data is also disclosed.
U.S. Pat. No. 5,926,414 to McDowell et al. teaches a magnetic integrated circuit structure in combination with a carrier-deflection-type magnetic field sensor. Each of a variety of magnet structures realize a condition in which the magnetic field is substantially orthogonal to the direction of travel of carriers of a sense current, thereby achieving maximum sensitivity. By basing a magnetic memory cell on a single minimum size MOS device, a small cell may be realized that compares favorably with a conventional DRAM of FLASH memory cell. The greater degree of control over the magnetic field afforded by the magnetic structures enables the cross-coupling between cells in a memory array to be minimized.
U.S. Pat. No. 3,727,199 to Lekven teaches a magnet memory element and a process for producing such elements in plurality to constitute a static magnetic memory or digital information storage system. Individual binary storage members are afforded directionally preferential magnetic characteristics by flux circuits to establish the preferred axids of magnetization. Conductors for driving the individual binary storage members (for storing and sensing) are provided in an organized pattern to accomplish selectivity. A batch production process is also disclosed.
None of the foregoing references disclose a non-volatile memory array wherein the remnant magnetic field is sensed with the same circuitry used to write, or effect the state change of a ferromagnetic bit in such a memory cell.